The present invention concerns transfer of data over an input/output bus and pertains particularly to solving a problem which arises using the Peripheral Component Interconnect (PCI) bus protocol (as set out in PCI Specification Version 2.1) to retrieve data from a (adaptive) "DEVSEL" device.
When utilizing Peripheral Component Interconnect (PCI) bus protocol (as set out in PCI Specification Version 2.1), if a particular target device cannot complete a data transfer within a predetermined time, the target device asserts a PCI STOP signal. This causes the initiator device to retry the data transfer at a later time. The initiator relinquishes the bus and when granted the bus, the initiator device retries the data transaction.
While waiting for the initiator device to retry the data transfer, the target device can get ready for the data transfer in order to complete the retry within the predetermined try. If the target device is an adaptive "DEVSEL" device, this means that on a retry, the target device will more quickly assert the DEVSEL signal indicating it is ready for a data transfer. For example, a target device which is adaptive "DEVSEL" device, when initially being selected as a target for a data transfer, will assert the DEVSEL signal for four PCI clock cycles after receiving a FRAME# signal. On a retry, the same adaptive "DEVSEL" device will assert the DEVSEL signal for two PCI clock cycles after receiving a FRAME# signal.
An example of an adaptive "DEVSEL" device is a PCI-to-Industry Standard Architecture (ISA) bridge such as a Intel 82371SB PCI-to-ISA bridge, available from Intel Corporation, having a business address of 2200 Mission College Boulevard, Santa Clara, Calif. 95050.
While use of an adaptive "DEVSEL" can increase the performance of a target device, there is a certain corner case where the use of an adaptive "DEVSEL" has the potential to cause a data transfer error. The present invention solves this corner case.